1. Field of the Invention
The invention relates to a direct memory access (DMA) system and, more particularly, to a unified DMA system adapted to various networking protocol such as WLAN, Ethernet, WiMAX, UWB, USB, and so on.
2. Description of the Prior Art
For any kind of high-performance network interface cards (NICs), a dedicated hardware for transferring TX/RX packets is widely used to improve the performance. Generally, this dedicated hardware utilizes the technology called direct memory access (DMA), which allows direct data transfer between certain interfaces and memories in a computer system without the intervention of central processing units (CPU).
Please refer to FIG. 1, which illustrates the operation flow of a conventional DMA device 10. When a CPU 12 plans to send a TX packet 14, it stores a buffer address 160 of the packet and some related packet information 162 into a TX descriptor 16 and then resets an associated owner bit 164. Subsequently, CPU 12 would inform DMA device 10 to move TX packet 14 from memory 18 to interface 20. After transmitting the TX packet 14, DMA device 10 sets owner bit 164 as 1 and inform CPU 12 that the transmission of TX packet 14 is finished.
When receiving an RX packet 22, CPU 12 allocates an available buffer space in memory 18 for the packet, stores a buffer address 240 into an RX descriptor 24, and then resets an associated owner bit 244. When the RX packet 22 is transferred from interface 20, DMA device 10 first checks the owner bit 244 of RX descriptor 24. Then, DMA device 10 transfers RX packet 22 from interface 20 to memory 18. After RX packet 22 is moved to memory 18, DMA device 10 writes a packet information 242 into the RX descriptor 24 and sets owner bit 244 as 1 and then informs CPU 12 of the completeness of receiving RX packet 22.
In order to improve the performance and reduce the requirement of First-In-First-Out (FIFO) memory, most conventional DMA devices support multiple TX/RX descriptors by, for instance, arranging descriptors as descriptor chains or descriptor rings. A typical TX descriptor chain is shown in FIG. 2, and a typical TX descriptor ring is shown in FIG. 3.
Although most DMA devices have similar operation rules, the designs of the DMA devices are not exactly the same. In particular, DMA devices will be different when the attached network media (e.g., Ethernet, WLAN, ADSL, WiMAX, and so on) changes. Therefore, when more and more interfaces are integrated into a system on chip (SoC), non-unified DMA descriptor architectures and semantic languages would increase hardware verification effort and software porting effort significantly. Moreover, different DMA engines for different interfaces are hard to maintain from the perspective of ASIC design.
Therefore, the scope of the invention is to provide a unified DMA system to solve the aforesaid problems.